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Multibit Recoding 기법과 Redundant Binary 연산을 이용한 병렬 승산기 설계

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dc.contributor.authorSHIN, KYUNG-WOOK-
dc.date.available2020-05-25T08:52:42Z-
dc.date.created2020-05-21-
dc.date.issued2000-09-
dc.identifier.urihttps://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/17540-
dc.publisher금오공대 산업기술개발연구원-
dc.titleMultibit Recoding 기법과 Redundant Binary 연산을 이용한 병렬 승산기 설계-
dc.title.alternativeA Design of parallel multiplier using multibit recoding and redundant binary arithmetic-
dc.typeArticle-
dc.contributor.affiliatedAuthorSHIN, KYUNG-WOOK-
dc.identifier.bibliographicCitation산업기술개발연구, v.16, no.3, pp.223 - 232-
dc.relation.isPartOf산업기술개발연구-
dc.citation.title산업기술개발연구-
dc.citation.volume16-
dc.citation.number3-
dc.citation.startPage223-
dc.citation.endPage232-
dc.type.rimsART-
dc.description.journalClass2-
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