A 125 MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle

Abstract

A 125 MHz 64-phase delay-locked loop (DLL) is implemented for time recovery in a digital wire-line system. The architecture of the proposed DLL comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200 MHz is fabricated using a 0.18-mu m 1-poly 6-metal CMOS process with a 1.8 V supply. The measured rms and peak-to-peak jitter of the output clock are 3.07 ps and 21.1 ps, respectively. The DNL and INL of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125 MHz. The area and power consumption of the implemented DLL are 0.3 mm(2) and 12.7 mW, respectively.