An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8 x 8 Point EEG/MEG Acquisition System
DC Field | Value | Language |
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dc.contributor.author | Eo, Ji-Hun | - |
dc.contributor.author | Jeong, Yeon-Ho | - |
dc.contributor.author | Jang, Young-Chan | - |
dc.date.available | 2020-04-24T12:25:59Z | - |
dc.date.created | 2020-03-31 | - |
dc.date.issued | 2013-02 | - |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/2169 | - |
dc.description.abstract | An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 8 x 8 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-mu m 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 mu W and 0.059 mm(2), respectively. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8 x 8 Point EEG/MEG Acquisition System | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Jang, Young-Chan | - |
dc.identifier.doi | 10.1587/transfun.E96.A.453 | - |
dc.identifier.scopusid | 2-s2.0-84873355949 | - |
dc.identifier.wosid | 000315244800007 | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E96A, no.2, pp.453 - 458 | - |
dc.citation.title | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.citation.volume | E96A | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 453 | - |
dc.citation.endPage | 458 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordAuthor | successive approximation | - |
dc.subject.keywordAuthor | analog-to-digital converter | - |
dc.subject.keywordAuthor | time-domain comparator | - |
dc.subject.keywordAuthor | daisy channel | - |
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