4.5 Gsymbol/s/lane MIPI C-PHY Receiver with Channel Mismatch Calibration

Abstract

A high-speed receiver that includes a clock recovery circuit is proposed to support mobile industry processor interface (MIPI) C-PHY version 2.0. The proposed MIPI C-PHY receiver uses a two-stage continuous-time linear equalizer and a level-dependent elastic buffer to compensate for the signal degraded due to channel attenuation and transition of three-level data. It performs calibration for mismatch between three channels for one lane of the MIPI C-PHY by adding three highspeed delay lines and calibration logic. In addition, a training pattern that transmitted from a MIPI C-PHY transmitter is proposed for the channel mismatch calibration. The proposed MIPI C-PHY receiver that supports a symbol rate of 4.5 Gsymbol/s/lane is designed by using a 40-nm CMOS process with a 1.1-V supply voltage. The proposed channel mismatch calibration reduces the peak-to-peak time jitter of the data and recovered clock by 25% and 31%, respectively.