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Low Hardware Complexity QCA Decoding Architecture Using Inverter Chain
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 전준철 | - |
| dc.date.accessioned | 2023-12-11T17:00:26Z | - |
| dc.date.available | 2023-12-11T17:00:26Z | - |
| dc.date.issued | 2016-04 | - |
| dc.identifier.issn | 2005-4297 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/25117 | - |
| dc.format.extent | 12 | - |
| dc.publisher | SERSC | - |
| dc.title | Low Hardware Complexity QCA Decoding Architecture Using Inverter Chain | - |
| dc.title.alternative | Low Hardware Complexity QCA Decoding Architecture Using Inverter Chain | - |
| dc.type | Article | - |
| dc.publisher.location | 대한민국 | - |
| dc.identifier.bibliographicCitation | International Journal of Control and Automation, v.9, no.4, pp 347 - 358 | - |
| dc.citation.title | International Journal of Control and Automation | - |
| dc.citation.volume | 9 | - |
| dc.citation.number | 4 | - |
| dc.citation.startPage | 347 | - |
| dc.citation.endPage | 358 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
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