A true single-phase clocked flip-flop with leakage current compensation
- Authors
- Lee, Han-Yeol; Jang, Young-Chan
- Issue Date
- 2012
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- true single-phase clocked flip-flop; leakage current
- Citation
- IEICE ELECTRONICS EXPRESS, v.9, no.23, pp.1807 - 1812
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 9
- Number
- 23
- Start Page
- 1807
- End Page
- 1812
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/2690
- DOI
- 10.1587/elex.9.1807
- ISSN
- 1349-2543
- Abstract
- A true single-phase clocked (TSPC) flip-flop, which compensates for the leakage current generated at dynamic nodes, is proposed to cover a wide operational frequency range in submicron CMOS processes. To implement the proposed TSPC flip-flop, three feedback circuits composed of a gated inverter (GI) are added to the conventional TSPC flip-flop. The GI is controlled by a clock and the internal signal of the conventional flip-flop, without an external control signal or a complementary clock signal. Furthermore, the strength ratio of the normal path to the feedback path does not need to be considered for the proposed TSPC flip-flop since the feedback circuit is only enabled when the dynamic node acquires a floating state. The proposed TSPC flip-flop is designed using a 1-poly 6-metal 65nm CMOS process with a 1V supply voltage. The simulation results show that the proposed TSPC flip-flop, which is optimized for normal operation at an operational frequency of 2 GHz, exhibits an error-free operation at low operational frequencies such as 1MHz. The three added feedback circuits increase the power consumption by 8.8% as compared to that of the conventional TSPC flip-flop and occupy 12.28% of the proposed flip-flop.
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