A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface
DC Field | Value | Language |
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dc.contributor.author | Eo, Ji-Hun | - |
dc.contributor.author | Kim, Sang-Hun | - |
dc.contributor.author | Jang, Young-Chan | - |
dc.date.available | 2020-04-24T13:25:29Z | - |
dc.date.created | 2020-03-31 | - |
dc.date.issued | 2011-11 | - |
dc.identifier.issn | 1745-1353 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/2695 | - |
dc.description.abstract | A 200 kS/s 10-bit successive approximation (SA) analog-to-digital converter (ADC) with a rail-to-rail input signal is proposed for acquiring biosignals such as EEG and MEG signals. A split-capacitor-based digital-to-analog converter (SC-DAC) is used to reduce the power consumption and chip area. The SC-DAC's linearity is improved by using dummy capacitors and a small bootstrapped analog switch with a constant on-resistance, without increasing its area. A time-domain comparator with a replica circuit for clock feed-through noise compensation is designed by using a highly differential digital architecture involving a small area. Its area is about 50% less than that of a conventional time-domain comparator. The proposed SA ADC is implemented by using a 0.18-mu m 1-poly 6-metal CMOS process with a I V supply. The measured DNL and INL are +0.44/-0.4 LSB and +0.71/-0.62 LSB, respectively. The SNDR is 55.43 dB for a 99.01 kHz analog input signal at a sampling rate of 200 kS/s. The power consumption and core area are 5 mu W and 0.126 mm(2), respectively. The FoM is 47 fJ/conversion-step. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Jang, Young-Chan | - |
dc.identifier.doi | 10.1587/transele.E94.C.1798 | - |
dc.identifier.scopusid | 2-s2.0-81255203482 | - |
dc.identifier.wosid | 000296673500016 | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E94C, no.11, pp.1798 - 1801 | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E94C | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 1798 | - |
dc.citation.endPage | 1801 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.subject.keywordAuthor | successive approximation | - |
dc.subject.keywordAuthor | analog-to-digital converter | - |
dc.subject.keywordAuthor | split-capacitor-based digital-to-analog converter | - |
dc.subject.keywordAuthor | time-domain comparator | - |
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