A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface
- Authors
- Jang, Young-Chan
- Issue Date
- Feb-2011
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- phase adjuster; phase skew; source synchronous double data rate signaling; time-domain reflectometry
- Citation
- IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E94A, no.2, pp.633 - 638
- Journal Title
- IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES
- Volume
- E94A
- Number
- 2
- Start Page
- 633
- End Page
- 638
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/2707
- DOI
- 10.1587/transfun.E94.A.633
- ISSN
- 0916-8508
- Abstract
- A self-calibrating per-pin phase adjuster, which does not feedback from the slave chip and a multi-phase clock in the master and slave chips, is proposed for a high speed parallel chip-to-chip interface with a source synchronous double data rate (DDR) signaling. It achieves not only per-pin phase adjustment but also 90 phase shift of a strobe signal for a source synchronous DDR signaling. For this self-calibration, the phase adjuster measures and compensates the only relative mismatched delay among channels by utilizing on-chip time-domain reflectometry (TDR). Thus, variable delay lines, finite state machines, and a test signal generator are additionally required for the proposed phase adjuster. In addition, the power-gating receiver is used to reduce the discontinuity effect of the channel including parasitic components of chip package. To verify the proposed self-calibrating per-pin phase adjuster, the transceivers with 16 data, strobe, and clock signals for the interface with a source synchronous DDR signaling were implemented by using a 60 nm 1-poly 3-metal CMOS DRAM process with a 1.5 V supply. Each phase skew between Strobe and 16 Data was corrected within 0.028UI at I.6-Gb/s data rate in a point-to-point channel.
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