An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system

Abstract

An unmatched source synchronous I/O link is proposed to reduce the time jitter of the sampling clocks for a receiver (RX) in a chip-to-chip interface system using a multi-phase clock. The proposed I/O link is initialized by two consecutive phase lock processes to optimize the RX sampling clocks. In the coarse lock process, the phase of the transmitted clock for a source synchronous I/O link is controlled by the resolution of the unit internal in the transmitter (TX) chip. The feedback path from the RX chip to the TX chip for the coarse lock information is merged into the normal path. The fine lock process is executed by a phase interpolator in the RX chip. The proposed I/O link reduces the latency and time jitter of RX sampling clocks by achieving the coarse lock process in the TX chip. To verify the proposed I/O link, a transceiver for a source synchronous I/O link clock with a quad data rate scheme was designed by using a 70 nm DRAM process with a 1.5 V supply. The proposed I/O link reduced the maximum jitter noise value by 42.4% in comparison to the jitter noise of a conventional multi-phase clock scheme.