11 -bit 1.8uW 40KS/s segmented SAR ADC for sensor applications

Abstract

This paper proposes an 11-b 40KS/s Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC) structure for sensor applications. Segmented structure is adopted in capacitive DAC to improve the linearity and decrease the power consumption. 500 aF custom-designed unit capacitors are applied in CDAC to reduce the area and to keep the ESX and DNL within 1 LSB of an 11 bit ADC. A prototype ADC was implemented in CMOS 0.18mm technology. This structure consumed 1.8jiW and achieved 67.27-dB SNDR and 83.7-dB SFDR at 40KS/s under a 1.8-V supply. The figure of merit (POM) was 37fJ/conversion-step. © 2016 IEEE.