Bulk-FinFETs implementing insulating layer under source and drain for DRAM cell application

Abstract

Partially-insulated oxide (PIOX) layers are implemented under the source/drain region in bulk FinFETs. The improved short channel effect by controlling the sub-channel on the bottom part of the gate in bulk FinFETs, the decreased junction leakage current due to blocking the vertical leakage path by PIOX layers, and the increased hot carrier lifetime can be applicable to future DRAM cell transistors.