ScholarWorks@SUNGKYUNKWAN UNIVERSITY: HAN, TAE HEE

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HAN, TAE HEE (한태희)

Information and Communication Engineering (Semiconductor Systems Engineering)

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networkonchip:7||Networkonchip:4||Throughput:3||Topology generation:3||application processor:3||thermal management:2||optical networkonchip (ONoC):2||optical router:2||hardware mapping based repair:2||touch screen panel:2||TSV:2||Bandwidth:2||Clock distribution:2||Throughsilicon via:2||builtin self test:2||metalmesh:2||insertion loss:2||mobile device:2||Routing:2||Routing protocols:2||Computational modeling:2||codebased repair:2||SOC:2||Computer architecture:2||dynamic self repair:2||genetic algorithm:2||Clock gating:1||Cmesh:1||Coherence:1||Compression:1||Compressive Sensing:1||Computational efficiency:1||Contention:1||Convolutional neural network:1||Custom topology:1||Custom topology generation:1||Customized networkonchip:1||DM:1||Data Reliability:1||Data transfer:1||Deep learning kernel:1||Delay modeling:1||Demapper:1||Dependency Analysis:1||Directorybased cache coherence protocol:1||Dual supply:1||Dynamic Thermal Management:1||Dynamic voltagefrequency island (DVFI):1||ECC controller:1||ECC mode:1||Energy optimization:1||Error Correcting Code:1||Error Pattern Modeling:1||FSM:1||Fattree topology:1||File System:1||Flow control:1||GALS:1||GEMM:1||Genetic algorithm:1||Genetic algorithms:1||Graph mining:1||HARQ:1||HONoC:1||Hamming codes:1||Hardened latch:1||High performance design:1||Huffman coding:1||Hybrid automatic repeat request (HARQ):1||I/O Scheduler:1||I/O buffer:1||I/O stack:1||IR Drop:1||IRdrop:1||Insertion loss:1||Integrated optics:1||Interconnection network:1||Latency:1||Ldi:1||Level converting:1||Licenses:1||Lifetime:1||Lifetime improvement:1||Linear optical device model (LODM):1||Link Power:1||Link failure:1||Logic Cone Analysis:1||Loglikelihood ratio (LLR):1||Longest Chain Length:1||Lowpower design:1||MPSK:1||Machine learning:1||Machine learning accelerator:1||Matrix multiply unit:1||Memory management:1||Multiple Expansion Scan Chain:1||Multithreading:1||Nearthreshold computing:1||Network topology:1||NetworkonChip (NoC):1||Networkonchip (NoC):1||Networkonchip(NoC):1||Networksonchip:1||Neural network:1||Neural network compression:1||Neural networks:1||NoC:1||ONoC:1||Optic:1||Optical crosstalk:1||Optical device fabrication:1||Optical noise:1||Optical propagation:1||Optimization:1||Parallel processing:1||Photonics:1||Post Silicon:1||Power Saving:1||Prefetching:1||Process Corner:1||Process Variation:1||Processinginmemory:1||Processor scheduling:1||Qfunction:1||Qlearning:1||QAM:1||Quadrature amplitude modulation (QAM):1||Quantization (signal):1||R:1||Random access memory:1||ReRAM:1||Reliability:1||SER:1||SSD:1||Schedules:1||Signal to noise ratio:1||Soft error:1||Standard cell library:1||System recovery:1||Systemonchip:1||Systolic array:1||TCU:1||TDM:1||Task analysis:1||Test Data Volume:1||Topology:1||Topology design:1||Training:1||Variation modeling:1||Vertical Throttling:1||Voltage Binning:1||VoltageFrequencyIsland (VFI):1||Voltagefrequency island:1||Voltagefrequency island (VFI):1||Voltage/frequency island:1||W interference:1||WAF:1||WDM:1||Wavelength routing:1||adaptive temperature scheduling:1||aging resilience:1||air gap:1||artificial intelligence:1||backsurface touch:1||binarized neural network:1||binarized neural networks:1||buffer sharing:1||bulk forward:1||cell characterisation:1||charge pump:1||clock frequency control:1||clock gating:1||common error conditions:1||communication energy:1||conventional error correction scheme:1||corrosion:1||crosstalk noise:1||custom topology generation:1||data migration:1||dead weight:1||deadlock recovery:1||deep neural network:1||demapper:1||diestacking:1||dielectric:1||directory caching:1||dt:1||dual supply:1||dynamic neural network:1||efficient computation:1||efficient machine learning:1||encoding:1||energy conservation:1||entropy encoding:1||error correction:1||error correction code:1||error correction codes:1||errorresilient router design:1||exploiting sparsity:1||fault tolerant:1||flash memory:1||frequent subgraph mining:1||garbage collection:1||gateoxide reliability:1||gating architecture:1||graph mining:1||heat dissipation:1||heterogeneous computing platform:1||heterogeneous manycore system:1||hotcarrier degradation:1||hybrid memory cube:1||hybrid optical networkonchip:1||hybrid optical networkonchip (HONoC):1||interconnect capacitance:1||intrachannel crosstalk:1||irregular topology:1||jamming:1||knowledge distillation:1||latchup:1||layer freezing:1||leakage current:1||level converting:1||loglikelihood ratio:1||lossless embedded compression (LEC):1||low battery condition:1||low power:1||lowpower electronics:1||machine learning accelerator:1||matrix multiply unit:1||memory bandwidth compression:1||microring resonator:1||mixedvoltage:1||model compression:1||multilevelcell:1||multicast communication:1||multicast routing:1||multiplevoltage multiplefrequency:1||networkonchips:1||neural network:1||optical interconnects:1||optical networkonchip:1||optimised doublebit errorcorrecting BCH code:1||optimizer:1||packet branching:1||page allocation:1||parallel computing:1||parameterized weight clipping:1||pathbased routing:1||phase effect:1||phasechange memory:1||physical design:1||power efficiency:1||power reduction:1||power supply network:1||power supply variation:1||powerefficient errorresilient networkonchip router:1||prediction:1||probable error conditions:1||process variation:1||reinforcement machine learning:1||reliability:1||residual transform:1||router:1||router architecture:1||routing:1||routing algorithm:1||runtime:1||runtime thermal management:1||selective error correction code scheme:1||semiconductor optical amplifier (SOA):1||sheet resistance:1||signaltonoise ratio:1||signaltonoise ratio (SNR):1||silicon photonics:1||singlebit errorcorrecting Hamming code:1||size 28:1||sparse directory:1||standard cell library:1||storage density:1||sudden voltage drop:1||superthreshold computing:1||systemlevel analysis:1||systemlevel design:1||systemonchip:1||systolic array:1||task scheduling:1||temperature estimation:1||thermal metamaterials:1||thermal property control:1||timing variation:1||topology generation:1||topology synthesis:1||transient errors:1||transparent:1||treebased routing:1||trilevelcell:1||virtual channel (VC) utilization:1||voltage and frequency tuning:1||voltage doubler:1||voltagefrequency island:1||waveguide crossing:1||wavelength allocation:1||배선 면적:1||전류 기반 로직 셀 배치:1||파워 게이팅:1||0 nm:1||파워 게이팅 셀 배치:1||3D NetworkonChip:1||3D NoC:1||3D integration:1||3D networkonchip:1||ASIC:1||Applicationspecific:1||Areaefficient design:1||Artificial intelligence:1||Asynchronous NetworkonChip (NoC):1||BCH code:1||BCH codes:1||BCH coding scheme:1||BEOL:1||BICM:1||Backpropagation:1||Bit interleaved coded modulation (BICM):1||BoseChaudhuriHocquenghem code:1||Bus protocol:1||CMOS integrated circuits:1||CPU:1||CPU performance:1||CSS:1||Cell library:1||Channel allocation:1||Circuit switching:1||

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(03063) 25-2, SUNGKYUNKWAN-RO, JONGNO-GU, SEOUL, KOREAsamsunglib@skku.edu

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