ScholarWorks@SUNGKYUNKWAN UNIVERSITY: CHO, HYUNG MIN

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CHO, HYUNG MIN (조형민)

Computing and Informatics (Computer Science and Engineering)

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SPICE:3||kNN:2||Computational modeling:2||Data models:2||Integrated circuit modeling:2||Machine learning (ML):2||Neardata processing:2||Optimization:2||Performance evaluation:2||Semiconductor device modeling:2||Semiconductor process modeling:2||Similarity Search:2||SolidState Drive:2||compact model:2||covert channel:2||network on chip:2||optimization:2||sampling:2||sub3nm device:2||technology computeraided design (TCAD):2||topology:2||Accelerators:1||machine learning (ML):1||Parity check codes:1||minimal aliasing code:1||RNN:1||Reliability:1||Algorithms:1||multibit upsets:1||nanosheet FETs:1||Signal processing algorithms:1||single error correction:1||Software:1||Software algorithms:1||soft errors:1||Systematics:1||TCAD/SPICE simulation:1||artificial neural network:1||binning:1||reinforcement learning:1||speculation:1||deep neural networks:1||deep neural networks (DNNs):1||Artificial neural network (ANN):1||depthwise convolution:1||DRAM chips:1||device modeling:1||Decoding:1||Error correction codes:1||Error resilience:1||FPGA:1||GPU:1||Hardware:1||Hybrid Platform:1||InDRAM error correcting code:1||emerging device:1||Licenses:1||field programmable gate arrays:1||Memory management:1||Memory modules:1||Monte Carlo Tree Search (MCTS):1||Multiplying circuits:1||

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