Unified all-digital duty-cycle and phase correction circuit for QDR I/O interface

Abstract

A unified all-digital duty-cycle and phase correction circuit, consisting of dual duty cycle corrector loops and one shared control block, is proposed for a quadrature data rate I/O interface. The proposed scheme makes four duty-corrected and phase-corrected phase clocks from two clocks of 08 and 908 using the sequential three steps correction. The use of a newly devised duty cycle detector, which is digitally operated without external reference voltage, is proposed. With simulated results using 0.18 mm CMOS technology, the output duty cycle is corrected to 50 + 0.4% as the input duty cycle ranges from 40 to 60%. The phase difference with the four-phase output clock is adjusted to 50 +/- 0.6% (250 +/- 3 ps) as the input phase-skew ranges from 40 to 60% (250 +/- 50 ps) at a frequency of 1 GHz.