Effect of Cu Pad Morphology on Direct-Cu Pillar Formation in CMOS Image Sensors

Abstract

We report the feasibility of forming Ni bumps directly on Cu pads in CMOS image sensor (CIS) logic elements formed by Cu wires with diameters of less than 65 nm. The direct Ni bump process proposed in this study simplifies the fabrication process and reduces costs by eliminating the need for Al pad process. In addition, this process can secure the margin of the final layer, enabling the realization of thin camera modules. In this study, we evaluated the effect of pad annealing on the direct formation of Ni bumps over Cu pads. The results suggest that the morphology of the Cu pad varies depending on the annealing sequence, and post-passivation annealing resulted in fewer defects than pad etch annealing. The shear stress of the Ni bumps was 57.77 mgf/m(2), which is six times greater than the corresponding reference value. Furthermore, we evaluated the reliability of a chip with an anisotropic conductive film (ACF) and a non-conducting paste (NCP) by using high-temperature storage (HTS), thermal cycling (TC), and wet high-temperature storage (WHTS) reliability tests. The evaluation results suggest the absence of abnormalities in all samples.