6-bit 1.6-GS/s 85-mW flash analog to digital converter using symmetric three-input comparator
- Authors
- Kim, Yun-Jeong; Lee, Jong-Ho; Koo, Ja-Hyun; Baek, Kwang-Hyun; Kim, Suki
- Issue Date
- Mar-2008
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- comparator flash ADC; high-speed ADC; interpolation
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, v.E91C, no.3, pp 392 - 395
- Pages
- 4
- Journal Title
- IEICE TRANSACTIONS ON ELECTRONICS
- Volume
- E91C
- Number
- 3
- Start Page
- 392
- End Page
- 395
- URI
- https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/23832
- DOI
- 10.1093/ietele/e91-c.3.392
- ISSN
- 0916-8524
1745-1353
- Abstract
- In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220 MHz at 1.6 GS/s, and almost five effective bits for 660 MHz input at 1.6 GS/s. Peak INL and DNL are less than 0.5 LSB and 0.45 LSB, respectively. This ADC consumes 85 mW from 1.8 V at 1.6 GS/s and occupies an active area of 0.27 mm(2). It is fabricated in 0.18-mu m CMOS.
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Collections - College of ICT Engineering > School of Electrical and Electronics Engineering > 1. Journal Articles
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