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Digitally controlled duty cycle corrector with 1 ps resolution

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dc.contributor.authorJo, Youngkwon-
dc.contributor.authorPark, Hoyoung-
dc.contributor.authorYang, Sanghyuk-
dc.contributor.authorKim, Suki-
dc.contributor.authorBaek, Kwang-Hyun-
dc.date.available2019-05-30T05:41:33Z-
dc.date.issued2007-09-
dc.identifier.issn0916-8524-
dc.identifier.urihttps://scholarworks.bwise.kr/cau/handle/2019.sw.cau/23997-
dc.description.abstractThis letter describes a digitally controlled duty cycle corrector (DCC) with 1 ps resolution. A new half period delay line (HPDL) control scheme using a delay locked loop (DLL) is proposed. The DCC has an output duty error less than 0.5% for 25% input duty error and operates correctly from 200 MHz to 800 MHz in a 0.18 mu m CMOS technology.-
dc.format.extent3-
dc.language영어-
dc.language.isoENG-
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG-
dc.titleDigitally controlled duty cycle corrector with 1 ps resolution-
dc.typeArticle-
dc.identifier.doi10.1093/ietele/e90-c.9.1841-
dc.identifier.bibliographicCitationIEICE TRANSACTIONS ON ELECTRONICS, v.E90C, no.9, pp 1841 - 1843-
dc.description.isOpenAccessN-
dc.identifier.wosid000250095300028-
dc.citation.endPage1843-
dc.citation.number9-
dc.citation.startPage1841-
dc.citation.titleIEICE TRANSACTIONS ON ELECTRONICS-
dc.citation.volumeE90C-
dc.type.docTypeArticle-
dc.publisher.location일본-
dc.subject.keywordAuthorduty cycle corrector-
dc.subject.keywordAuthorvariable delay unit-
dc.subject.keywordAuthordelay locked loop-
dc.subject.keywordPlusLOOP-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
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