Current-loop Gate Driving Circuit for Solid-state Marx Modulator with Fast-rising Nanosecond Pulses
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, S.-H. | - |
dc.contributor.author | Song, S.-H. | - |
dc.contributor.author | Ryoo, H.-J. | - |
dc.date.accessioned | 2021-08-17T05:40:13Z | - |
dc.date.available | 2021-08-17T05:40:13Z | - |
dc.date.issued | 2021-08 | - |
dc.identifier.issn | 0885-8993 | - |
dc.identifier.issn | 1941-0107 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/48495 | - |
dc.description.abstract | When designing solid-state Marx modulators (SSMMs) with fast-rising nanosecond pulses, the gate driving scheme for pulse discharge switches is one of the most important aspects to be considered. In this study, we propose a nanosecond current-loop gate driving circuit for a synchronized fast gate drive of pulse discharge switches. The proposed circuit comprises an inverter, a current-loop cable, and discharge switch drivers. The inverter generates bipolar pulses that simultaneously provide driving power and fast triggering signals to all discharge switch drivers through the cable. The triggered discharge switch drivers rapidly turn on/off all discharge switches with accurate synchronization. In the inverter and discharge switch drivers, the fast gate-driving methods were used to overcome parasitic inductances and realize nanosecond operation. The concept and operational principles of the proposed gate driving scheme are presented. To validate the performance and reliability of the SSMM using the proposed current-loop gate driving circuit, a laboratory test on a 10-kV–70-A–50-kHz SSMM prototype was conducted, and the results were discussed. IEEE | - |
dc.format.extent | 9 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Current-loop Gate Driving Circuit for Solid-state Marx Modulator with Fast-rising Nanosecond Pulses | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TPEL.2021.3051041 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Power Electronics, v.36, no.8, pp 8953 - 8961 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000649673800039 | - |
dc.identifier.scopusid | 2-s2.0-85099575587 | - |
dc.citation.endPage | 8961 | - |
dc.citation.number | 8 | - |
dc.citation.startPage | 8953 | - |
dc.citation.title | IEEE Transactions on Power Electronics | - |
dc.citation.volume | 36 | - |
dc.type.docType | Article | - |
dc.publisher.location | 미국 | - |
dc.subject.keywordAuthor | Capacitors | - |
dc.subject.keywordAuthor | Discharges (electric) | - |
dc.subject.keywordAuthor | Fast risetime | - |
dc.subject.keywordAuthor | gate driving circuit | - |
dc.subject.keywordAuthor | Insulated gate bipolar transistors | - |
dc.subject.keywordAuthor | Inverters | - |
dc.subject.keywordAuthor | Logic gates | - |
dc.subject.keywordAuthor | narrow pulse width | - |
dc.subject.keywordAuthor | solid-state Marx modulator | - |
dc.subject.keywordAuthor | Switches | - |
dc.subject.keywordAuthor | Synchronization | - |
dc.subject.keywordPlus | Cables | - |
dc.subject.keywordPlus | Electric inverters | - |
dc.subject.keywordPlus | Modulators | - |
dc.subject.keywordPlus | Timing circuits | - |
dc.subject.keywordPlus | Discharge switches | - |
dc.subject.keywordPlus | Fast gate drive | - |
dc.subject.keywordPlus | Nanosecond pulse | - |
dc.subject.keywordPlus | Operational principles | - |
dc.subject.keywordPlus | Parasitic inductances | - |
dc.subject.keywordPlus | Performance and reliabilities | - |
dc.subject.keywordPlus | Pulse discharge | - |
dc.subject.keywordPlus | Triggering signal | - |
dc.subject.keywordPlus | Ultrafast lasers | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
84, Heukseok-ro, Dongjak-gu, Seoul, Republic of Korea (06974)02-820-6194
COPYRIGHT 2019 Chung-Ang University All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.