A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS
DC Field | Value | Language |
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dc.contributor.author | Yeoh, Hong Chang | - |
dc.contributor.author | Jung, Jae-Hun | - |
dc.contributor.author | Jung, Yun-Hwan | - |
dc.contributor.author | Baek, Kwang-Hyun | - |
dc.date.accessioned | 2021-09-01T01:41:05Z | - |
dc.date.available | 2021-09-01T01:41:05Z | - |
dc.date.issued | 2010-09 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.issn | 1558-173X | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/48982 | - |
dc.description.abstract | This paper presents a low-power direct digital frequency synthesizer (DDFS) based on a hybrid design with a maximum operating frequency of 1.3 GHz. The proposed hybrid design is capable of extending the resolution of traditional nonlinear digital-to-analog converter (DAC)-based DDFS by adding a linear slope component to the approximated sine wave produced from a nonlinear DAC via an additional linear DAC. With an 11-bit combined DAC, the prototype DDFS produces a minimum spurious free dynamic range (SFDR) of 52 dBc from dc up to Nyquist frequency when clocked at 1.3 GHz. This 90-nm CMOS chip occupies 2 mm(2) including bond pads and dissipates 350 mW with a 1.2-V digital supply and 2.5-V analog supply. The FOM of this chip is measured at 1207.9 GHz . 2(ENOB)/W. | - |
dc.format.extent | 11 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2010.2056830 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.45, no.9, pp 1845 - 1855 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000283166300019 | - |
dc.identifier.scopusid | 2-s2.0-77956213079 | - |
dc.citation.endPage | 1855 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 1845 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 45 | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.publisher.location | 미국 | - |
dc.subject.keywordAuthor | CMOS direct digital frequency synthesizer (DDFS) | - |
dc.subject.keywordAuthor | digital-to-analog converter (DAC) | - |
dc.subject.keywordAuthor | pipelined accumulator | - |
dc.subject.keywordAuthor | segmented nonlinear DAC | - |
dc.subject.keywordPlus | INP DHBT TECHNOLOGY | - |
dc.subject.keywordPlus | 0.18-MU-M SIGEBICMOS TECHNOLOGY | - |
dc.subject.keywordPlus | SINE-WEIGHTED DAC | - |
dc.subject.keywordPlus | CLOCK FREQUENCY | - |
dc.subject.keywordPlus | NONLINEAR DAC | - |
dc.subject.keywordPlus | CONVERTER | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | sci | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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