An FPGA-based parallel accelerator for matrix multiplications in the Newton-Raphson method
DC Field | Value | Language |
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dc.contributor.author | Xu, X. | - |
dc.contributor.author | Ziavras, S.G. | - |
dc.contributor.author | Chang, T.-G. | - |
dc.date.accessioned | 2022-01-11T03:40:31Z | - |
dc.date.available | 2022-01-11T03:40:31Z | - |
dc.date.issued | 2005-12 | - |
dc.identifier.issn | 0302-9743 | - |
dc.identifier.issn | 1611-3349 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/53235 | - |
dc.description.abstract | Power flow analysis plays an important role in power grid configurations, operating management and contingency analysis. The Newton-Raphson (NR) iterative method is often enlisted for solving power flow analysis problems. However, it involves computation-expensive matrix multiplications (MMs). In this paper we propose ail FPGA-based Hierarchical-SIMD (H-SIMD) machine with its codesign of the Hierarchical Instruction Set Architecture (HISA) to speed up MM within each NR iteration. FPGA stands for Field-Programmable Gate Array. HISA is comprised of medium-grain and coarse-grain instructions. The H-SIMD machine also facilitates better mapping of MM onto recent multimillion-gate FPGAs. At each level, any HISA instruction is classified to be of either the communication or computation type. The former are executed by a controller while the latter are issued to lower levels in the hierarchy. Additionally, by using a memory switching scheme and the high-level HISA set to partition applications, the host-FPGA communication overheads can be hidden. Our test results show sustained high performance. | - |
dc.format.extent | 11 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | SPRINGER-VERLAG BERLIN | - |
dc.title | An FPGA-based parallel accelerator for matrix multiplications in the Newton-Raphson method | - |
dc.type | Article | - |
dc.identifier.doi | 10.1007/11596356_47 | - |
dc.identifier.bibliographicCitation | EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005, v.3824, pp 458 - 468 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000234715700044 | - |
dc.identifier.scopusid | 2-s2.0-33744960829 | - |
dc.citation.endPage | 468 | - |
dc.citation.startPage | 458 | - |
dc.citation.title | EMBEDDED AND UBIQUITOUS COMPUTING - EUC 2005 | - |
dc.citation.volume | 3824 | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.publisher.location | 독일 | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Software Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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