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A Preliminary Study: Towards Parallel Garbage Collection for NAND Flash-Based SSDs

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dc.contributor.authorZhu, Guangyu-
dc.contributor.authorHan, Jaehyun-
dc.contributor.authorSon, Yongseok-
dc.date.accessioned2022-01-20T06:41:48Z-
dc.date.available2022-01-20T06:41:48Z-
dc.date.issued2020-12-
dc.identifier.issn2169-3536-
dc.identifier.urihttps://scholarworks.bwise.kr/cau/handle/2019.sw.cau/54005-
dc.description.abstractNAND Flash-based solid-state drives (SSDs) have been widely used as secondary storage devices due to their faster access speed, lower power consumption, and higher reliability compared with hard disk drives. However, application I/O performance can be significantly affected by garbage collection (GC) inside SSDs. For example, a GC operation usually moves valid pages from a victim block into a clean block in a serialized manner. Thus, it increases the GC time and affects the application I/O performance. To address this issue, this article presents a preliminary study on a parallel GC scheme for flash-based SSDs. In our scheme, we parallelize valid page migrations during a GC operation to reduce the total GC time. To do this, we first propose a new flash chip architecture that enables valid page migrations in parallel. Second, we collect information such as new addresses for the migration of valid pages by considering the restriction of SSD operations. Finally, we employ multiple worker threads to migrate the valid pages using the collected information in a parallel manner. We implement and evaluate our scheme using Disksim with Microsoft SSD extension. The experimental result shows that the proposed scheme reduces the overall GC time by 70% and 57% on average compared with the existing scheme and a state-of-the-art GC scheme IPPBE, respectively.-
dc.format.extent14-
dc.language영어-
dc.language.isoENG-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Preliminary Study: Towards Parallel Garbage Collection for NAND Flash-Based SSDs-
dc.typeArticle-
dc.identifier.doi10.1109/ACCESS.2020.3043123-
dc.identifier.bibliographicCitationIEEE ACCESS, v.8, pp 223574 - 223587-
dc.description.isOpenAccessN-
dc.identifier.wosid000603722700001-
dc.identifier.scopusid2-s2.0-85097938189-
dc.citation.endPage223587-
dc.citation.startPage223574-
dc.citation.titleIEEE ACCESS-
dc.citation.volume8-
dc.type.docTypeArticle-
dc.publisher.location미국-
dc.subject.keywordAuthorRegisters-
dc.subject.keywordAuthorComputer architecture-
dc.subject.keywordAuthorParallel processing-
dc.subject.keywordAuthorMicroprocessors-
dc.subject.keywordAuthorDegradation-
dc.subject.keywordAuthorComputer science-
dc.subject.keywordAuthorTemperature distribution-
dc.subject.keywordAuthorGarbage collection-
dc.subject.keywordAuthorNAND flash memory-
dc.subject.keywordAuthorparallelism-
dc.subject.keywordAuthorsolid-state drive-
dc.subject.keywordPlusSOLID-STATE DRIVES-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordPlusPOLICY-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
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