A 3.2-GHz 178-fs <formula> <tex>_rms</tex> </formula> Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier
DC Field | Value | Language |
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dc.contributor.author | Yoon, D. | - |
dc.contributor.author | Jung, D. | - |
dc.contributor.author | Seong, K. | - |
dc.contributor.author | Han, J. | - |
dc.contributor.author | Chung, K. | - |
dc.contributor.author | Kim, J. | - |
dc.contributor.author | Kim, T.T. | - |
dc.contributor.author | Baek, Kwang Hyun | - |
dc.date.accessioned | 2022-06-10T02:40:06Z | - |
dc.date.available | 2022-06-10T02:40:06Z | - |
dc.date.issued | 2022-07 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.issn | 1557-9999 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/58258 | - |
dc.description.abstract | This article proposes a 3.2-GHz subsampling phase-locked loop (SSPLL)-based injection-locked clock multiplier (ILCM) using a subsampling delay-locked loop (SSDLL). The proposed ILCM achieves a superior noise reduction effect at low offset frequency because of the high feedback gain of SSPLL. Also, SSDLL is proposed for background phase calibration between SSPLL and injection. Since SSPLL and SSDLL use identical SSCP, the power consumption of the frequency and phase calibration is only 1.32 mW. This work is fabricated in a 65-nm CMOS process, and the 10-kHz phase noise is improved by 8.6 dB. The rms jitter from 10 kHz to 30 MHz is 178 fs. The chip-to-chip variations (20 chips) are 17 and 169 fs with/without SSDLL, respectively. The measured results show that FoM&#x2081;, FoM&#x2082;, and total power consumption are -245.1, -260.1 dB, and 9.85 mW, respectively. IEEE | - |
dc.format.extent | 11 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A 3.2-GHz 178-fs <formula> <tex>_rms</tex> </formula> Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TVLSI.2022.3169636 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.30, no.7, pp 915 - 925 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000799607100001 | - |
dc.identifier.scopusid | 2-s2.0-85130444424 | - |
dc.citation.endPage | 925 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 915 | - |
dc.citation.title | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | - |
dc.citation.volume | 30 | - |
dc.type.docType | Article | - |
dc.publisher.location | 미국 | - |
dc.subject.keywordAuthor | Calibration | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | Delay-locked loop (DLL) | - |
dc.subject.keywordAuthor | Delays | - |
dc.subject.keywordAuthor | injection-locked clock multiplier (ILCM) | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | low noise | - |
dc.subject.keywordAuthor | Phase locked loops | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | subsampling PLL (SSPLL). | - |
dc.subject.keywordAuthor | Transfer functions | - |
dc.subject.keywordAuthor | Voltage-controlled oscillators | - |
dc.subject.keywordPlus | SUB-SAMPLING PLL | - |
dc.subject.keywordPlus | ALL-DIGITAL PLL | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | SYNTHESIZER | - |
dc.subject.keywordPlus | DIVIDER | - |
dc.subject.keywordPlus | FAMILY | - |
dc.subject.keywordPlus | LOOP | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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