A switch wrapper design for SNA on-chip-network
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, J.H. | - |
dc.contributor.author | Yi, J.S. | - |
dc.contributor.author | Kim, J. | - |
dc.date.accessioned | 2023-03-09T00:42:17Z | - |
dc.date.available | 2023-03-09T00:42:17Z | - |
dc.date.issued | 2005 | - |
dc.identifier.issn | 0302-9743 | - |
dc.identifier.issn | 1611-3349 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/65537 | - |
dc.description.abstract | In this paper we present a design of a switch wrapper as a component of SNA (SoC network architecture), which is an efficient on-chip-network compared to a shared bus architecture in a SoC. The SNA uses crossbar routers to provide the increasing demand on communication bandwidth within a single chip. A switch wrapper for SNA is located between a crossbar router and IN connecting them together. It carries out a mode of routing to assist crossbar routers and executes protocol conversions to provide compatibility in IP reuse. A switch wrapper consists of a direct router, two AHB-SNP converters, two interface sockets and a controller module. We implement it in VHDL. Using ModelSim simulation, we confirm the functionality of the switch wrapper. We synthesize it using a Xilinx Virtex2 device to determine resource requirements: The switch wrapper seems to occupy appropriate spaces, about 900 gates, considering that a single SNA crossbar router costs about 20,000 gates. | - |
dc.format.extent | 10 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | SPRINGER-VERLAG BERLIN | - |
dc.title | A switch wrapper design for SNA on-chip-network | - |
dc.type | Article | - |
dc.identifier.doi | 10.1007/11572961_32 | - |
dc.identifier.bibliographicCitation | ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS, v.3740, pp 405 - 414 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000234508800032 | - |
dc.identifier.scopusid | 2-s2.0-33646496325 | - |
dc.citation.endPage | 414 | - |
dc.citation.startPage | 405 | - |
dc.citation.title | ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS | - |
dc.citation.volume | 3740 | - |
dc.type.docType | Article; Proceedings Paper | - |
dc.publisher.location | 독일 | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
84, Heukseok-ro, Dongjak-gu, Seoul, Republic of Korea (06974)02-820-6194
COPYRIGHT 2019 Chung-Ang University All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.