Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kyung, Y. | - |
dc.contributor.author | Kim, G.S. | - |
dc.contributor.author | Baek, D. | - |
dc.date.accessioned | 2023-08-18T01:41:25Z | - |
dc.date.available | 2023-08-18T01:41:25Z | - |
dc.date.issued | 2022-12 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/67352 | - |
dc.description.abstract | This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-μm CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are −204.3, −211.07, −220.29, and −213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively. | - |
dc.format.extent | 11 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Institute of Electronics Engineers of Korea | - |
dc.title | Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems | - |
dc.type | Article | - |
dc.identifier.doi | 10.5573/JSTS.2022.22.6.482 | - |
dc.identifier.bibliographicCitation | Journal of Semiconductor Technology and Science, v.22, no.6, pp 482 - 492 | - |
dc.identifier.kciid | ART002906587 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000907562800010 | - |
dc.identifier.scopusid | 2-s2.0-85144634276 | - |
dc.citation.endPage | 492 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 482 | - |
dc.citation.title | Journal of Semiconductor Technology and Science | - |
dc.citation.volume | 22 | - |
dc.type.docType | Article | - |
dc.publisher.location | 대한민국 | - |
dc.subject.keywordAuthor | Clock generator | - |
dc.subject.keywordAuthor | low jitter | - |
dc.subject.keywordAuthor | multiplying delay locked loop (MDLL) | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | reference-sampling PLL (RSPLL) | - |
dc.subject.keywordAuthor | sub-sampling PLL (SSPLL) | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
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