Converting Interfaces on Application-specific Network-on-chip
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, Kyuseung | - |
dc.contributor.author | Lee, Jae-Jin | - |
dc.contributor.author | Lee, Woojoo | - |
dc.date.accessioned | 2024-01-09T04:34:16Z | - |
dc.date.available | 2024-01-09T04:34:16Z | - |
dc.date.issued | 2017-08 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/cau/handle/2019.sw.cau/69912 | - |
dc.description.abstract | As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC. | - |
dc.format.extent | 9 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Converting Interfaces on Application-specific Network-on-chip | - |
dc.type | Article | - |
dc.identifier.doi | 10.5573/JSTS.2017.17.4.505 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.17, no.4, pp 505 - 513 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.wosid | 000410980300004 | - |
dc.identifier.scopusid | 2-s2.0-85028770996 | - |
dc.citation.endPage | 513 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 505 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 17 | - |
dc.type.docType | Article | - |
dc.publisher.location | 대한민국 | - |
dc.subject.keywordAuthor | Network-on-chip | - |
dc.subject.keywordAuthor | NoC | - |
dc.subject.keywordAuthor | application-specific NoC | - |
dc.subject.keywordAuthor | SoC | - |
dc.subject.keywordAuthor | processor | - |
dc.subject.keywordAuthor | computer architecture | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | AWARE | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
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