Effect of Double Epitaxial Layer on the Latch-Up Immunity in High-Power Devices

Abstract

We report on the improved latch-up immunity of high-voltage devices fabricated using P-/P++ double-layer epitaxy on a P- substrate without degradation in the electrostatic discharge or electrical parameters for LV, MV, and HV MOSFETs. Backseal polysilicon and backseal oxide were not applied to lower the process cost. The resistivity of P++ epi was fixed at the level of the commercial epi wafer's P++ substrate and that of the P- epi layer at the level of the resistivity of the prime wafer used for this product. Only the thickness of the P- epi layer was split to obtain the optimum condition in order to improve the latch-up immunity without degradation in the electrostatic discharge or other electrical parameters of the transistors. We characterized the boron doping profile uniformity within the wafer after P-/P++ double-layer epi deposition via SIMS.