Effect of Interface Treatment on the Voltage Linearity in 8 fF mu m(2) High-k Dielectric and Combination Stacks on Metal Insulator Metal (MIM) Capacitor

Abstract

Manufacturable, cost-effective 8-fF/mu m(2) metal-insulator-metal (MIM) capacitors were integrated with dielectrics by using plasma enhanced-atomic layer deposition (PE-ALD) and the Al interconnect process to obtain analog/mixed signal technology. The voltage linearity was evaluated not only by carrying out an interface treatment for the metal electrode and insulator dielectrics but also through the combined stack structure of high-k and SiO2 dielectrics. In the Al2O3/HfO2/Al2O3 (AHA) stack layer, the plasma treatment of the bottom electrode prior to insulator deposition improved the voltage linearity. In the SiO2/HfO2 (SH) stack layer, an increase in the thickness ratio of SiO2 was a dominant factor in improving the voltage linearity. There was no initial failure in a preliminary test of the voltage ramp dielectric breakdown (VRDB) for the AHA stack MIM capacitors.