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SCIESCOPUS
Device and circuit interactive design and optimization beyond the conventional scaling eraGo to Link

Oh, Saeroonter; Wei, Lan; Chong, Soogine; Luo, Jieying; Wong, H.-S.Philip

ArticleIssue Date2010CitationTechnical Digest - International Electron Devices Meeting, IEDM, pp.1 - 1PublisherIEEE
SCIESCOPUS
Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling ApproachGo to Linkopen access

Lee, Ji Hwan; Kim, Kihwan; Rim, Kyungjin; Chong, Soogine; Cho, Hyunbo; Oh, Saeroonter

ArticleIssue Date2024CitationIEEE Journal of the Electron Devices Society, v.12, pp 770 - 774PublisherInstitute of Electrical and Electronics Engineers Inc.
SCOPUS
Performance Evaluation of Strain Effectiveness of Sub-5 nm GAA FETs with Compact Modeling based on Neural NetworksGo to Link

Lee, Ji Hwan; Kim, Kihwan; Rim, Kyungjin; Chong, Soogine; Cho, Hyunbo; Oh, Saeroonter

ArticleIssue Date2023Citation7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023, pp 1 - 3PublisherInstitute of Electrical and Electronics Engineers Inc.
SCIESCOPUS
Technology Projection Using Simple Compact ModelsGo to Link

Wong, H-S. Philip; Wei, Lan; Oh, Saeroonter; Lin, Albert; Deng, Jie; Chong, Soogine; Akarvardar, Kerem

ArticleIssue Date2009CitationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD, pp 1 - 8PublisherIEEE
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