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IPsec for high speed network links: Performance analysis and enhancements

Authors
Ullah, SamiChoi, JoontaeOh, Heekuck
Issue Date
Jun-2020
Publisher
ELSEVIER
Keywords
IPsec; High speed network links security; Performance analysis; Bottlenecks in IPsec; DPDK
Citation
FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE, v.107, pp 112 - 125
Pages
14
Indexed
SCIE
SCOPUS
Journal Title
FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE
Volume
107
Start Page
112
End Page
125
URI
https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/1065
DOI
10.1016/j.future.2020.01.049
ISSN
0167-739X
1872-7115
Abstract
Network packets security has always been significantly important and well researched topic but the network throughput and latency are not optimal on high speed network links, when using existing IPsec solutions. Network packet processing in Linux kernel is significantly slow (especially for 10-G/40-G link speed) due to context switching associated with system calls, and transitional copy operations in packet traversal through all network layers. Control plane layered packet processing involve copy operation per layer, which increases the packet processing time and consequently decreases the throughput of the network. In contrast to the kernel networking, data plane solutions like DPDK (Data Plane Development Kit) provide direct access to packets (from NIC) in user-space bypassing kernel stack, with zero intermediate copy operations and no context switching. For the normal packets, Intel DPDK claims 10x improvement in the throughput over kernel networking. Being inspired by that remarkable efficiency, we have done empirical evaluation of IPsec performance in data plane. Towards this goal, primarily we have analyzed the performance effect by individual bottleneck modules of strongSwan (an IPsec implementation); by redesigning them with data plane equivalent modules. Secondarily, we have proposed an efficient solution for strongSwan using DPDK API; which eliminates all previously identified bottleneck modules. In the proposed design, multi-cores design has been incorporated in the crypto module and performance is analyzed in terms of throughput and latency. There is an improvement of up to 3.54x in throughput and 2.54x improvement in latency as compared to existing control plane design. With AES128GCM as encryption scheme, a maximum throughput of 4.795 Gbps is achieved, while using only two cores. (C) 2020 Elsevier B.V. All rights reserved.
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ERICA 소프트웨어융합대학 (ERICA 컴퓨터학부)
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