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Multi-class Data Description 기반의 웨이퍼 빈 맵 불량 패턴 분류 및 신규 불량 패턴 검출방법

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dc.contributor.author송창용-
dc.contributor.author정영선-
dc.contributor.author김병훈-
dc.date.accessioned2022-07-04T06:40:05Z-
dc.date.available2022-07-04T06:40:05Z-
dc.date.issued2022-06-
dc.identifier.issn1225-0988-
dc.identifier.issn2234-6457-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/107552-
dc.description.abstractIn the semiconductor manufacturing process, electrical die sorting(EDS) test is a process to check whether the individual chips have reached the desired quality level by performing electrical property inspection on each semiconductor chip on a wafer. After performing the EDS test, a human expert can check the spatial defect pattern of wafer bin map(WBM) that displays the defectiveness of each chip. Since the defect patterns of WBMs are analyzed to trace back the processes and facilities for root cause analysis, it is very important to classify the WBM defect patterns. Because most existing studies use a classification model that trains predefined defect patterns, there is a limitation in that it cannot detect a new defect pattern that is not included in the training dataset. In this study, a method for classifying predefined defect patterns and detecting undefined defect patterns is proposed based on the multi-class data description model. As a result of the evaluation using actual WBM data, it was confirmed that it has excellent performance in classifying existing defect patterns and detecting new defect patterns.-
dc.format.extent12-
dc.language한국어-
dc.language.isoKOR-
dc.publisher대한산업공학회-
dc.titleMulti-class Data Description 기반의 웨이퍼 빈 맵 불량 패턴 분류 및 신규 불량 패턴 검출방법-
dc.title.alternativeA Multi-Class Data Description Based Method for Classifying Predefined Defect Patterns and Detecting New Defect Patterns of Wafer Bin Maps-
dc.typeArticle-
dc.publisher.location대한민국-
dc.identifier.doi10.7232/JKIIE.2022.48.3.298-
dc.identifier.bibliographicCitation대한산업공학회지, v.48, no.3, pp 298 - 309-
dc.citation.title대한산업공학회지-
dc.citation.volume48-
dc.citation.number3-
dc.citation.startPage298-
dc.citation.endPage309-
dc.identifier.kciidART002847453-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClasskci-
dc.subject.keywordAuthorSemiconductor-
dc.subject.keywordAuthorWafer Bin Map-
dc.subject.keywordAuthorDefect Pattern Classification-
dc.subject.keywordAuthorNew Defect Pattern Detection-
dc.subject.keywordAuthorMulti-Class Data Description-
dc.identifier.urlhttps://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE11074791-
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ERICA 공학대학 (DEPARTMENT OF INDUSTRIAL & MANAGEMENT ENGINEERING)
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