A 0.9-mu A Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive Feed-Forward Ripple Cancellation Technique

Abstract

This article presents a high power supply rejection ratio (PSRR) low dropout (LDO) regulator with a low quiescent current. A low quiescent current capacitive feed-forward ripple cancellation (CFFRC) technique is proposed to cancel the power supply noise. With this technique, low power consumption is achieved via feed-forward capacitors and back-to-back pseudo-resistors bias. This design was fabricated using the 0.18-mu m CMOS technology. The entire proposed LDO consumes a quiescent current of 0.9 mu A. Compared with an LDO without enhancement, at the maximum load current of 200 mA, the measured PSRR has an enhancement of -22 dB at 1 MHz.