An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Dongjun | - |
dc.contributor.author | Park, Gijin | - |
dc.contributor.author | Han, Jaeduk | - |
dc.contributor.author | Choo, Min-Seong | - |
dc.date.accessioned | 2023-03-13T04:43:48Z | - |
dc.date.available | 2023-03-13T04:43:48Z | - |
dc.date.issued | 2023-01 | - |
dc.identifier.issn | 2169-3536 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/111607 | - |
dc.description.abstract | This paper presents a design automation methodology for ring voltage-controlled oscillators (RVCOs) with their realistic and physical characteristics captured. With multiple sets of input constraints such as target frequency, phase noise, and control voltage range, the proposed algorithm automatically finds the design candidates that satisfy the target constraints, by running iterative post-layout simulations with auto-generated layouts and testbenches. The number of post-layout simulations is significantly reduced by the backtracking algorithm that observes the simulation results and determines the search direction. The proposed algorithm is applied to generate RVCOs in 40-nm planar and 7-nm FinFET technologies for DDR5 applications, and it turns out the proposed methodology produces sets of design parameters that meet the target specification in multiple technologies. | - |
dc.format.extent | 10 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/ACCESS.2022.3232960 | - |
dc.identifier.scopusid | 2-s2.0-85146252318 | - |
dc.identifier.wosid | 000923837000001 | - |
dc.identifier.bibliographicCitation | IEEE Access, v.11, pp 7530 - 7539 | - |
dc.citation.title | IEEE Access | - |
dc.citation.volume | 11 | - |
dc.citation.startPage | 7530 | - |
dc.citation.endPage | 7539 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | LOCKED CLOCK MULTIPLIER | - |
dc.subject.keywordPlus | PHASE NOISE | - |
dc.subject.keywordPlus | OPTIMIZATION | - |
dc.subject.keywordPlus | JITTER | - |
dc.subject.keywordPlus | ANALOG | - |
dc.subject.keywordPlus | RANGE | - |
dc.subject.keywordPlus | VCO | - |
dc.subject.keywordPlus | PVT | - |
dc.subject.keywordAuthor | Layout | - |
dc.subject.keywordAuthor | Ring oscillators | - |
dc.subject.keywordAuthor | Phase noise | - |
dc.subject.keywordAuthor | Latches | - |
dc.subject.keywordAuthor | Design methodology | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | CMOS technology | - |
dc.subject.keywordAuthor | FinFETs | - |
dc.subject.keywordAuthor | design automation | - |
dc.subject.keywordAuthor | layout generation | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | frequency control | - |
dc.subject.keywordAuthor | phase noise | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/10002363 | - |
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