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Electrolyte-Gated Vertical Synapse Array based on Van Der Waals Heterostructure for Parallel Computing

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dc.contributor.authorOh Seyong-
dc.contributor.authorLee Ju-Hee-
dc.contributor.authorSeo Seunghwan-
dc.contributor.authorChoo Hyongsuk-
dc.contributor.authorLee Dongyoung-
dc.contributor.authorCho Jeong-Ick-
dc.contributor.authorPark Jin-Hong-
dc.date.accessioned2023-07-05T05:30:04Z-
dc.date.available2023-07-05T05:30:04Z-
dc.date.issued2022-02-
dc.identifier.issn2198-3844-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/112833-
dc.description.abstractRecently, three-terminal synaptic devices, which separate read and write terminals, have attracted significant attention because they enable nondestructive read-out and parallel-access for updating synaptic weights. However, owing to their structural features, it is difficult to address the relatively high device density compared with two-terminal synaptic devices. In this study, a vertical synaptic device featuring remotely controllable weight updates via e-field-dependent movement of mobile ions in the ion-gel layer is developed. This synaptic device successfully demonstrates all essential synaptic characteristics, such as excitatory/inhibitory postsynaptic current (E/IPSC), paired-pulse facilitation (PPF), and long-term potentiation/depression (LTP/D) by electrical measurements, and exhibits competitive LTP/D characteristics with a dynamic range (G(max)/G(min)) of 31.3, and asymmetry (AS) of 8.56. The stability of the LTP/D characteristics is also verified through repeated measurements over 50 cycles; the relative standard deviations (RSDs) of G(max)/G(min) and AS are calculated as 1.65% and 0.25%, respectively. These excellent synaptic properties enable a recognition rate of approximate to 99% in the training and inference tasks for acoustic and emotional information patterns. This study is expected to be an important foundation for the realization of future parallel computing networks for energy-efficient and high-speed data processing.-
dc.format.extent10-
dc.language영어-
dc.language.isoENG-
dc.publisherWiley-VCH Verlag-
dc.titleElectrolyte-Gated Vertical Synapse Array based on Van Der Waals Heterostructure for Parallel Computing-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1002/advs.202103808-
dc.identifier.scopusid2-s2.0-85121738247-
dc.identifier.wosid000734295700001-
dc.identifier.bibliographicCitationAdvanced Science, v.9, no.6, pp 1 - 10-
dc.citation.titleAdvanced Science-
dc.citation.volume9-
dc.citation.number6-
dc.citation.startPage1-
dc.citation.endPage10-
dc.description.isOpenAccessY-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaChemistry-
dc.relation.journalResearchAreaScience & Technology - Other Topics-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalWebOfScienceCategoryChemistry, Multidisciplinary-
dc.relation.journalWebOfScienceCategoryNanoscience & Nanotechnology-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.subject.keywordPlusDEVICES-
dc.subject.keywordPlusHETEROJUNCTION-
dc.subject.keywordPlusUPDATE-
dc.subject.keywordAuthorhardware artificial neural networks-
dc.subject.keywordAuthorion gel-
dc.subject.keywordAuthorparallel computing-
dc.subject.keywordAuthorsynapse arrays-
dc.subject.keywordAuthorvan der Waals heterostructures-
dc.subject.keywordAuthorvertical synaptic devices-
dc.identifier.urlhttps://www.scopus.com/record/display.uri?eid=2-s2.0-85121738247&origin=inward&txGid=d016b56c2936a5d0da7b36cf84e7e40b-
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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