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Simulation of a Recessed Channel Ferroelectric-Gate Field-Effect Transistor with a Dual Ferroelectric Gate Stack for Memory Application
- Authors
- Chen, Simin; Ahn, Dae-Hwan; Ui An, Seong; Kim, Younghyun
- Issue Date
- Apr-2023
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Keywords
- FeFET; ferroelectric recessed channel; MFMFMIS
- Citation
- 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023, pp 1 - 3
- Pages
- 3
- Indexed
- SCOPUS
- Journal Title
- 7th IEEE Electron Devices Technology and Manufacturing Conference: Strengthen the Global Semiconductor Research Collaboration After the Covid-19 Pandemic, EDTM 2023
- Start Page
- 1
- End Page
- 3
- ISSN
- 0000-0000
- Abstract
- Over the years, there has been much research on ferroelectric field-effect transistors (FeFETs) for memory applications. In this work, we propose a novel recessed channel FeFET with gate metal-ferroelectric (FE)- metal-FE-metal-SiO2 interlayer (IL)-silicon (MFMFMIS) gate stack, which is named a dual ferroelectric recessed channel FeFET (DF-RFeFET) aimed to increase the memory window (MW) for high-performance memory applications. With calibrated FE parameters and device models in technology computer-aided design (TCAD) simulation, we found that the DF-RFeFET can have a large MW of 3.2 V. In addition, guidelines for the DF-RFeFET design are provided in terms of the thickness ratio of the inner and outer FE layers to maximize the MW. © 2023 IEEE.
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Related Researcher
- Kim, Young hyun
- ERICA 첨단융합대학 (ERICA 반도체·디스플레이공학전공)