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Design of a Host Interface Logic for GC-Free SSDs

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dc.contributor.authorJung, Myoungsoo-
dc.contributor.authorChoi, Wonil-
dc.contributor.authorKwon, Miryeong-
dc.contributor.authorSrikantaiah, Shekhar-
dc.contributor.authorYoo, Joonhyuk-
dc.contributor.authorKandemir, Mahmut Taylan-
dc.date.accessioned2023-08-16T07:37:38Z-
dc.date.available2023-08-16T07:37:38Z-
dc.date.issued2020-08-
dc.identifier.issn0278-0070-
dc.identifier.issn1937-4151-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/113950-
dc.description.abstractGarbage collection (GC) and resource contention on I/O buses (channels) are among the critical bottlenecks in solid-state drives (SSDs) that cannot be easily hidden. Most existing I/O scheduling algorithms in the host interface logic (HIL) of state-of-the-art SSDs are oblivious to such low-level performance bottlenecks in SSDs. As a result, SSDs may violate quality of service (QoS) requirements by not being able to meet the deadlines of I/O requests. In this paper, we propose a novel host interface I/O scheduler that is both GC aware and QoS aware. The proposed scheduler redistributes the GC overheads across noncritical I/O requests and reduces channel resource contention. Our experiments with workloads from various application domains revealed that the proposed client-level SSD scheduler reduces the standard deviation for latency by 52.5% and the worst-case latency by 86.6%, compared to the state-of-the-art I/O schedulers used for the HIL. In addition, for I/O requests smaller than a superpage, the proposed scheduler avoids channel resource conflicts and reduces latency by 29.2% in comparison to the state-of-the-art I/O schedulers. Furthermore, we present an extension of the proposed I/O scheduler for enterprise SSDs based on the NVMe protocol.-
dc.format.extent14-
dc.language영어-
dc.language.isoENG-
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleDesign of a Host Interface Logic for GC-Free SSDs-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/TCAD.2019.2919035-
dc.identifier.scopusid2-s2.0-85067013878-
dc.identifier.wosid000550655600011-
dc.identifier.bibliographicCitationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.39, pp 1674 - 1687-
dc.citation.titleIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems-
dc.citation.volume39-
dc.citation.startPage1674-
dc.citation.endPage1687-
dc.type.docType정기학술지(Article(Perspective Article포함))-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryComputer Science, Interdisciplinary Applications-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusFLASH TRANSLATION LAYER-
dc.subject.keywordPlusGARBAGE COLLECTION-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusMEMORY-
dc.subject.keywordAuthorGarbage collection (GC)-
dc.subject.keywordAuthorhost interface-
dc.subject.keywordAuthorsolid-state disk (SSD)-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8723109?arnumber=8723109&SID=EBSCO:edseee-
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ERICA 소프트웨어융합대학 (ERICA 컴퓨터학부)
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