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Soft error study on DDR4 SDRAMs using a 480 MeV proton beam

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dc.contributor.authorPark, Myungsang-
dc.contributor.authorJeon, Sanghoon-
dc.contributor.authorBak, Geunyong-
dc.contributor.authorLim, Chulseung-
dc.contributor.authorBaeg, Sanghyeon-
dc.contributor.authorWen, Shijie-
dc.contributor.authorWong, Richard-
dc.contributor.authorYu, Nick-
dc.date.accessioned2021-06-22T15:24:15Z-
dc.date.available2021-06-22T15:24:15Z-
dc.date.created2021-01-22-
dc.date.issued2017-04-
dc.identifier.issn1541-7026-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/11665-
dc.description.abstractThis paper is a soft error study on logic upset in control logic, using a 480 MeV proton beam on commercial DDR4 SDRAM components from two different manufacturers. Samples with the same density and speed showed a 1.9x difference in logic cross section depending on the manufacturer. Compared to DDR3 SDRAM, DDR4 SDRAM from the same manufacturer showed about 45% SBU cross-section increase, and 17% logic upset decrease. To understand how the storage capacitance of down-scaling DDR technologies affects soft error, soft error bits were compared to retention weak bits. No evidence was found that indicated that retention weak bits were more sensitive to soft error. © 2017 IEEE.-
dc.language영어-
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleSoft error study on DDR4 SDRAMs using a 480 MeV proton beam-
dc.typeArticle-
dc.contributor.affiliatedAuthorBaeg, Sanghyeon-
dc.identifier.doi10.1109/IRPS.2017.7936404-
dc.identifier.scopusid2-s2.0-85025162825-
dc.identifier.wosid000416068500152-
dc.identifier.bibliographicCitationIEEE International Reliability Physics Symposium Proceedings, pp.1 - 6-
dc.relation.isPartOfIEEE International Reliability Physics Symposium Proceedings-
dc.citation.titleIEEE International Reliability Physics Symposium Proceedings-
dc.citation.startPage1-
dc.citation.endPage6-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusDynamic random access storage-
dc.subject.keywordPlusErrors-
dc.subject.keywordPlusManufacture-
dc.subject.keywordPlusProton beams-
dc.subject.keywordPlusRadiation hardening-
dc.subject.keywordPlusDDR technology-
dc.subject.keywordPlusDDR4 SDRAM-
dc.subject.keywordPlusDown-scaling-
dc.subject.keywordPlusIn-control-
dc.subject.keywordPluslogic upset cluster-
dc.subject.keywordPlusSingle event upsets-
dc.subject.keywordPlusSoft error-
dc.subject.keywordPlusStorage capacitance-
dc.subject.keywordPlusComputer circuits-
dc.subject.keywordAuthorDDR4 SDRAM-
dc.subject.keywordAuthorlogic upset cluster-
dc.subject.keywordAuthorretention weak bits-
dc.subject.keywordAuthorsingle event upset-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/7936404-
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