Heterogeneous 3-D Sequential CFETs With Ge (110) Nanosheet p-FETs on Si (100) Bulk n-FETs

Abstract

In this study, we report on the fabrication and characterization of 3-D sequential complementary field-effect-transistors (CFETs) using the direct wafer bonding (DWB) technology and a low-temperature process for monolithic 3-D (M3D) integration. The device features a high-performance top Ge (110)/<inline-formula> <tex-math notation=LaTeX>$\langle$</tex-math> </inline-formula>110<inline-formula> <tex-math notation=LaTeX>$\rangle$</tex-math> </inline-formula> channel on a bottom Si CMOS. To ensure high performance without causing damage to the bottom Si n-FETs, the maximum thermal budget during the fabrication of the top Ge p-FETs was limited to 400 <inline-formula> <tex-math notation=LaTeX>$^{\circ}$</tex-math> </inline-formula>C. We systematically investigated the mobility enhancement of the thin Ge (110) nanosheet (NS) channel p-FETs as a function of channel orientation. Our results demonstrate that the low effective hole mass along the <inline-formula> <tex-math notation=LaTeX>$\langle$</tex-math> </inline-formula>110<inline-formula> <tex-math notation=LaTeX>$\rangle$</tex-math> </inline-formula> direction on Ge (110) wafer provides record-high mobility of 400 cm<inline-formula> <tex-math notation=LaTeX>$^{\text{2}}$</tex-math> </inline-formula>/V<inline-formula> <tex-math notation=LaTeX>$\cdot$</tex-math> </inline-formula>s (corresponding to 760 cm<inline-formula> <tex-math notation=LaTeX>$^{\text{2}}$</tex-math> </inline-formula>/V<inline-formula> <tex-math notation=LaTeX>$\cdot$</tex-math> </inline-formula>s when normalized by footprint) at room temperature, which is the highest reported among the Ge p-FETs with similar channel thicknesses. IEEE