Architecture-Aware Currying
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kandemir, Mahmut Taylan | - |
dc.contributor.author | Akbulut, Gulsum Gudukbay | - |
dc.contributor.author | 최원일 | - |
dc.contributor.author | Karakoy, Mustafa | - |
dc.date.accessioned | 2024-04-01T01:00:16Z | - |
dc.date.available | 2024-04-01T01:00:16Z | - |
dc.date.issued | 2023-10 | - |
dc.identifier.issn | 1089-795X | - |
dc.identifier.issn | 1089-795X | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/118321 | - |
dc.description.abstract | In near-data computing (NDC), computation is brought into data, as opposed to bringing data to computation. While there is prior work focusing on different NDC opportunities, there is no study, to our knowledge, that investigates the importance of "neighborhood" in NDC. This paper explores the neighborhood concept in multithreaded programs that run on on-chip network-based manycore systems. We define the concept of "neighborhood", in terms of on-chip network links, and use it to formulate the NDC problem. We propose a "generic" compiler algorithm, called "architecture-aware currying", that uses the neighborhood concept to implement NDC. So, a core can perform some portions of computation with the nearby data and postpone the remainder of the computation until the remaining data become nearby. It can also perform computations - with nearby data - on behalf of other cores. Our experimental evaluation shows that the proposed compiler algorithm outperforms state-of-the-art data locality optimization strategies. | - |
dc.format.extent | 15 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.title | Architecture-Aware Currying | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/PACT58117.2023.00029 | - |
dc.identifier.scopusid | 2-s2.0-85182593301 | - |
dc.identifier.wosid | 001165646800021 | - |
dc.identifier.bibliographicCitation | 2023 32ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT, pp 250 - 264 | - |
dc.citation.title | 2023 32ND INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PACT | - |
dc.citation.startPage | 250 | - |
dc.citation.endPage | 264 | - |
dc.type.docType | Proceedings Paper | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Software Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.subject.keywordPlus | MEMORY | - |
dc.subject.keywordPlus | LOCALITY | - |
dc.subject.keywordAuthor | currying | - |
dc.subject.keywordAuthor | optimizing compilers | - |
dc.subject.keywordAuthor | data locality | - |
dc.subject.keywordAuthor | distance-to-data | - |
dc.subject.keywordAuthor | manycore systems | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/10364569 | - |
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