3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Gijin | - |
dc.contributor.author | Yeom, Sunoh | - |
dc.contributor.author | Jang, In-Woo | - |
dc.contributor.author | Lee, Dongjun | - |
dc.contributor.author | Han, Jaeduk | - |
dc.contributor.author | Choo, Min-Seong | - |
dc.date.accessioned | 2024-06-11T00:00:30Z | - |
dc.date.available | 2024-06-11T00:00:30Z | - |
dc.date.issued | 2024-04 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.issn | 1558-3791 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/119262 | - |
dc.description.abstract | This brief solves the challenge of loop latency in the digital filter of conventional digital phase-locked loops (DPLLs), which hinders timely updates of phase frequency detector error information. To address this latency problem, we introduce a direct path for jitter correction, utilizing a pulse generator with an adaptive pulse width controller (PWC). The impact of PWC-based phase correction is analyzed to optimize the proportional gain in DPLLs. The DPLL, designed with adaptive gain control and realized in 40-nm CMOS technology, significantly enhances its performance metrics. Operating from a 100-MHz reference clock to produce a 3.2-GHz output, the prototype achieves a power consumption of 6.36 mW. Remarkably, the measurements indicate a 25% improvement in integrated jitter, reduced from 1231 to 942 fs, while maintaining comparable reference spur performance relative to conventional DPLL designs. | - |
dc.format.extent | 5 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | 3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/TCSII.2024.3392771 | - |
dc.identifier.scopusid | 2-s2.0-85191324397 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Circuits and Systems II: Express Briefs, pp 1 - 5 | - |
dc.citation.title | IEEE Transactions on Circuits and Systems II: Express Briefs | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 5 | - |
dc.type.docType | Article in press | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Jitter | - |
dc.subject.keywordPlus | Phase locked loops | - |
dc.subject.keywordPlus | Calculators | - |
dc.subject.keywordPlus | Timing | - |
dc.subject.keywordPlus | Circuits | - |
dc.subject.keywordPlus | Quantization (signal) | - |
dc.subject.keywordPlus | Phase noise | - |
dc.subject.keywordAuthor | Adaptive loop gain control (ALGC) | - |
dc.subject.keywordAuthor | autocorrelation | - |
dc.subject.keywordAuthor | Calculators | - |
dc.subject.keywordAuthor | Circuits | - |
dc.subject.keywordAuthor | digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | direct proportional path | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | Phase locked loops | - |
dc.subject.keywordAuthor | Phase noise | - |
dc.subject.keywordAuthor | pulse width control (PWC) | - |
dc.subject.keywordAuthor | Quantization (signal) | - |
dc.subject.keywordAuthor | Timing | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/10507171 | - |
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