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LDO regulator with high power supply rejection at 10MHz
- Authors
- Javed, Khurram; Roh, Jeongjin
- Issue Date
- Dec-2016
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- low-dropout regulator; power supply rejection; negative capacitance
- Citation
- IEICE ELECTRONICS EXPRESS, v.13, no.24, pp.1 - 6
- Indexed
- SCIE
SCOPUS
- Journal Title
- IEICE ELECTRONICS EXPRESS
- Volume
- 13
- Number
- 24
- Start Page
- 1
- End Page
- 6
- ISSN
- 1349-2543
- Abstract
- A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of -67.9 dB at 10 MHz.
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Related Researcher
- Roh, Jeong jin
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)