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LAYOUT COMPACTION FOR HIGH-PERFORMANCE/LARGE-SCALE CIRCUITS
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Shin, Hyunchul | - |
| dc.date.accessioned | 2025-03-07T02:30:27Z | - |
| dc.date.available | 2025-03-07T02:30:27Z | - |
| dc.date.issued | 2024-01 | - |
| dc.identifier.issn | 978100357 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/122234 | - |
| dc.description.abstract | Layout compaction is the process of converting a symbolic layout or a sketch of a topological layout to a design-rule-correct mask layout with minimal area. It can be used in module generators as well as in postprocessors for placement and routing systems. Since manual compaction is tedious and error-prone, automatic layout compaction can significantly improve layout productivity and allow designers to explore more design alternatives in symbolic or functional level. © 1996 by Taylor & Francis Group, LLC. | - |
| dc.format.extent | 33 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | CRC Press | - |
| dc.title | LAYOUT COMPACTION FOR HIGH-PERFORMANCE/LARGE-SCALE CIRCUITS | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1201/9781003575245-9 | - |
| dc.identifier.scopusid | 2-s2.0-85208908105 | - |
| dc.identifier.bibliographicCitation | Advanced Routing of Electronic Modules, pp 313 - 345 | - |
| dc.citation.title | Advanced Routing of Electronic Modules | - |
| dc.citation.startPage | 313 | - |
| dc.citation.endPage | 345 | - |
| dc.type.docType | Book chapter | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.identifier.url | https://www.taylorfrancis.com/chapters/edit/10.1201/9781003575245-9/layout-compaction-high-performance-large-scale-circuits-hyunchul-shin | - |
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