Automatic Layout Decomposition for DPT

Abstract

Automatic layout decomposition techniques have been developed for double patterning technology (DPT). As CMOS manufacturing process scales down to 65nm and below, lithography resolution needs to be improved. DPT has been proposed to enhance the limitation of conventional lithography, by decomposing the layout design into two masks to relax the minimum spacing requirement. However, it is not always possible to decompose a layout into two masks. We have developed new automatic stitching techniques to resolve this problem. Experimental results show that the suggested techniques are promising in decomposing layouts for DPT.