테스트 핀 축소에 의한 저비용 SoC 테스트 구조

Abstract

In this paper a reduced pin count SoC test architecture using IEEE 1149.1 and IEEE 1500 wrapper is presented. By using only a small number of test pins low cost automated test equipments (ATEs) can be efficiently utilized to SoC test cost. Experimental results show that the SoC test time can be significantly reduced by performing multi-site test.