An Efficient Interconnect Test Patterns for Crosstalk and Static Faults

Abstract

In this paper, we present efficient test patterns for the crosstalk–induced faults on System-on-a-Chip and board level interconnects considering actual effective aggressors to minimize the pattern size. All static faults also can be detected. The proposed method achieved the significant reduction of the number of test patterns than prior works, while preserving 100% fault coverage. We are in the process of extending the proposed technique to built-in-self test logics.