Flit-Partitioned Parallel Test Technique for NoC Based SoCs

Abstract

Reusing on-chip functional interconnects as test access mechanism (TAM) appeared natural these days. One of the most important functional interconnects for highly crowded future SoCs is Network-on-Chip (NoC). Till date different kinds of synchronous, asynchronous NoC architectures, router and network interface (NI) architectures have been proposed, to allow multicast of packets, in-order packet delivery, guaranteed throughput and best-effort services. Exploiting these features, we present here a flit-partitioned parallel test technique for NoC based SoCs while reusing NoC as TAM, to reduce the test time.