Crosstalk cancelling voltage-mode driver for multi-Gbps parallel DRAM interface
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Younghoon | - |
dc.contributor.author | Yoo, Changsik | - |
dc.date.accessioned | 2021-06-22T19:21:58Z | - |
dc.date.available | 2021-06-22T19:21:58Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2015-09 | - |
dc.identifier.issn | 0098-9886 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/17389 | - |
dc.description.abstract | For multi-Gb/s/pin parallel dynamic random access memory (DRAM) interface, a crosstalk cancelling voltage-mode driver is proposed. The voltage-mode driver is composed of a main driver and sub-drivers where the cancellation signal is generated by the sub-drivers. The outputs of the main driver and sub-drivers are combined by a capacitive coupling so the direct current (DC) output swing is not affected by the crosstalk cancellation and the sub-drivers may not consume DC power. The proposed crosstalk cancelling voltage-mode driver implemented in a 0.11-mu m complementary metal-oxide semiconductor (CMOS) technology improves the horizontal eye openings by 22.6ps at 4-Gbps/pin. Copyright (c) 2014 John Wiley & Sons, Ltd. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | WILEY | - |
dc.title | Crosstalk cancelling voltage-mode driver for multi-Gbps parallel DRAM interface | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Younghoon | - |
dc.identifier.doi | 10.1002/cta.2003 | - |
dc.identifier.scopusid | 2-s2.0-84941185109 | - |
dc.identifier.wosid | 000360767800005 | - |
dc.identifier.bibliographicCitation | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, v.43, no.9, pp.1175 - 1182 | - |
dc.relation.isPartOf | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | - |
dc.citation.title | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS | - |
dc.citation.volume | 43 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 1175 | - |
dc.citation.endPage | 1182 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | crosstalk | - |
dc.subject.keywordAuthor | crosstalk induced jitter | - |
dc.subject.keywordAuthor | single-ended signalling | - |
dc.subject.keywordAuthor | voltage-mode driver | - |
dc.subject.keywordAuthor | DRAM | - |
dc.subject.keywordAuthor | CMOS | - |
dc.identifier.url | https://onlinelibrary.wiley.com/doi/10.1002/cta.2003 | - |
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