Scan-Puf: Puf Elements Selection Methods for Viable IC Identification
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dooyoung | - |
dc.contributor.author | Ansari, Mahammad Adil | - |
dc.contributor.author | Jung, Jihun | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-22T21:43:18Z | - |
dc.date.available | 2021-06-22T21:43:18Z | - |
dc.date.issued | 2015-11 | - |
dc.identifier.issn | 1081-7735 | - |
dc.identifier.issn | 2377-5386 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/20611 | - |
dc.description.abstract | The scan PUF, which is based-on the power-up states of scan flip-flops, had been proposed to overcome security issues of semiconductor ICs. IC identification, one of those security issues, requires decent uniqueness along with reliability and randomness. This paper presents two efficient PUF elements' selection methods for scan PUF: uniqueunanimous selection method and unique-majority selection method. These methods classify the scan cells according to their trend of power-up states and prioritize them to extract PUF elements. For experiments, enrollment and validation is performed on 15 chips, which are fabricated with 65nm CMOS process. A statistical analysis on experiments verifies the performance of proposed selection methods. © 2015 IEEE. | - |
dc.format.extent | 6 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE Computer Society | - |
dc.title | Scan-Puf: Puf Elements Selection Methods for Viable IC Identification | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/ATS.2015.28 | - |
dc.identifier.scopusid | 2-s2.0-84963569048 | - |
dc.identifier.wosid | 000386184700021 | - |
dc.identifier.bibliographicCitation | Proceedings of the Asian Test Symposium, pp 121 - 126 | - |
dc.citation.title | Proceedings of the Asian Test Symposium | - |
dc.citation.startPage | 121 | - |
dc.citation.endPage | 126 | - |
dc.type.docType | Conference Paper | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | CMOS integrated circuits | - |
dc.subject.keywordPlus | Flip flop circuits | - |
dc.subject.keywordPlus | Hardware security | - |
dc.subject.keywordPlus | 65nm cmos | - |
dc.subject.keywordPlus | Elements selection | - |
dc.subject.keywordPlus | Physically unclonable functions | - |
dc.subject.keywordPlus | Scan cells | - |
dc.subject.keywordPlus | Scan flip-flops | - |
dc.subject.keywordPlus | scan PUF | - |
dc.subject.keywordPlus | Security issues | - |
dc.subject.keywordPlus | Selection methods | - |
dc.subject.keywordPlus | Scanning | - |
dc.subject.keywordAuthor | hardware security | - |
dc.subject.keywordAuthor | IC identificaion | - |
dc.subject.keywordAuthor | physically unclonable function | - |
dc.subject.keywordAuthor | scan PUF | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/7422246 | - |
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