Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Jaehoon | - |
dc.contributor.author | Jung, Jihun | - |
dc.contributor.author | Kim, Dooyoung | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-22T23:23:06Z | - |
dc.date.available | 2021-06-22T23:23:06Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2014-06 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/22834 | - |
dc.description.abstract | Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.5573/JSTS.2014.14.3.345 | - |
dc.identifier.scopusid | 2-s2.0-84903743940 | - |
dc.identifier.wosid | 000338934400010 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.14, no.3, pp.345 - 355 | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 14 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 345 | - |
dc.citation.endPage | 355 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART001887547 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | SYSTEM CHIPS | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordAuthor | AMBA | - |
dc.subject.keywordAuthor | system-on-a-chip | - |
dc.subject.keywordAuthor | scan test | - |
dc.subject.keywordAuthor | IEEE 1500 | - |
dc.subject.keywordAuthor | parallel test | - |
dc.subject.keywordAuthor | test time | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE02501183&language=ko_KR&hasTopBanner=true | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
55 Hanyangdeahak-ro, Sangnok-gu, Ansan, Gyeonggi-do, 15588, Korea+82-31-400-4269 sweetbrain@hanyang.ac.kr
COPYRIGHT © 2021 HANYANG UNIVERSITY. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.