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Effective datapath logic extraction techniques using connection vectors

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dc.contributor.authorWang, Yu-
dc.contributor.authorYeo, Donghoon-
dc.contributor.authorShin, Hyunchul-
dc.date.accessioned2021-06-22T09:42:14Z-
dc.date.available2021-06-22T09:42:14Z-
dc.date.created2021-01-21-
dc.date.issued2019-09-
dc.identifier.issn1751-858X-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/2331-
dc.description.abstractDatapath macros are essential components of integrated circuits. The high regularity of datapaths allows compact layout design during placement. In some cases, datapath macros are manually pre-designed and pre-placed. However, datapath macros are frequently mixed with other circuits and they need to be extracted to capitalise on their regularity. In this study, the cells of a given circuit are accurately classified based on their size and pin information, and novel connection vectors to represent aspects of the connectivity among the cells have been proposed. By using the connection vectors of the cells, the similarity of connections is evaluated to extract potential datapath stages that constitute functional steps of a datapath. Two new efficient datapath logic extraction techniques (EDLETs) have been implemented based on the connection vectors for extracting potential datapaths in the circuit. One is the procedure-based method, and the other is the machine learning-based method. When compared with state-of-the-art methods, the experiments show that both the procedure-based and the learning-based methods proposed in this study efficiently extract potential datapaths from the Modified International Symposium on Physical Design (MISPD) 2011 Datapath Benchmark Suite. The extraction results of the proposed EDLET can be forwarded to a datapath placement tool for placing datapaths with a regular structure.-
dc.language영어-
dc.language.isoen-
dc.publisherINST ENGINEERING TECHNOLOGY-IET-
dc.titleEffective datapath logic extraction techniques using connection vectors-
dc.typeArticle-
dc.contributor.affiliatedAuthorShin, Hyunchul-
dc.identifier.doi10.1049/iet-cds.2018.5083-
dc.identifier.scopusid2-s2.0-85073163913-
dc.identifier.wosid000537293500002-
dc.identifier.bibliographicCitationIET CIRCUITS DEVICES & SYSTEMS, v.13, no.6, pp.741 - 747-
dc.relation.isPartOfIET CIRCUITS DEVICES & SYSTEMS-
dc.citation.titleIET CIRCUITS DEVICES & SYSTEMS-
dc.citation.volume13-
dc.citation.number6-
dc.citation.startPage741-
dc.citation.endPage747-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusSTRUCTURE-AWARE PLACEMENT-
dc.subject.keywordPlusHOTSPOT DETECTION-
dc.subject.keywordPlusDESIGNS-
dc.subject.keywordAuthorintegrated circuit layout-
dc.subject.keywordAuthorlearning (artificial intelligence)-
dc.subject.keywordAuthorlogic design-
dc.subject.keywordAuthorlogic circuits-
dc.subject.keywordAuthorMISPD 2011 Datapath Benchmark Suite-
dc.subject.keywordAuthordatapath placement tool-
dc.subject.keywordAuthorconnection vectors-
dc.subject.keywordAuthordatapath macros-
dc.subject.keywordAuthorintegrated circuits-
dc.subject.keywordAuthorcompact layout design-
dc.subject.keywordAuthormachine learning-
dc.subject.keywordAuthordatapath logic extraction-
dc.subject.keywordAuthorpin information-
dc.subject.keywordAuthordatapath stages-
dc.identifier.urlhttps://ietresearch.onlinelibrary.wiley.com/doi/10.1049/iet-cds.2018.5083-
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