Analysis of a Multiple Cell Upset Failure Model for Memories

Abstract

As technology shrinks, Multiple Cell Upsets (MCU) are becoming a more prominent effect with a large impact on memory reliability. The use of single error correction codes (SEC) and interleaving is the most common approach to protect memories from MCUs. In the last years several models have been proposed to evaluate reliability of memories that use SEC and interleaving in the presence of MCUs. In a recent paper some of the authors proposed an analytical model for the failure probability of a memory suffering MCUs. In this paper the analytical model is first validated by simulation showing a good agreement between the model and simulation experiments based on the model assumptions. Then the effects of some constraints imposed in derivation of the model are evaluated by comparing the model results with simulations experiments on which those constraints are removed. This comparison illustrates the accuracy of the model and can be useful for designers that plan to use the model to evaluate memory reliability.